1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more particularly, to a time-domain voltage comparator for an analog-to-digital converter which can convert voltage differences into time differences.
2. Description of the Related Art
In general, an analog-to-digital converter (ADC) is a circuit for converting an analog signal into a digital signal and is used as one of essential blocks not only in the field of wireless communication but also in all the fields of signal processing.
In particular, in the case of application fields, such as a portable terminal or a wireless sensor network, in which power supply depends on a battery and therefore available energy is extremely limited, it is essential to decrease a supply voltage and minimize power consumption.
In this regard, if the supply voltage is decreased, the reliability of an analog circuit markedly deteriorates when compared to a digital circuit, and therefore, a problem is caused in that the stable operation of an analog-to-digital converter cannot be ensured.
FIG. 1 is a block diagram illustrating a conventional fully-differential analog-to-digital converter.
Referring to FIG. 1, a conventional fully-differential analog-to-digital converter 100 includes a first digital-to-analog converter (DAC) 110, a second digital-to-analog converter 120, a comparator 130 which is configured to compare input voltages outputted from the converters 110 and 120, and a successive approximation register (SAR) 140.
Operation of the conventional fully-differential analog-to-digital converter 100 will be described with reference to FIG. 1.
First, the first digital-to-analog converter 110 and the second digital-to-analog converter 120 convert digital signals into analog voltages and output the analog voltages. The comparator 130 compares the magnitude of the output voltage of the first digital-to-analog converter 110 and the magnitude of the output voltage of the second digital-to-analog converter 120.
Then, as a result of the comparison, the comparator 130 outputs information about which one of the magnitudes is greater, as one digital value.
A time-domain voltage comparator stands for a voltage comparator which does not directly compare two input voltages, converts the respective input voltages into information for times, and compares the times.
While this kind of comparator has been introduced on the ISSCC in 2008, excellent results have not been obtained with respect to reducing a voltage of supply power and an offset.
FIG. 2 is a circuit diagram illustrating a conventional time-domain voltage comparator.
Referring to FIG. 2, a conventional time-domain voltage comparator 200 includes a first voltage-to-time converter 210, a second voltage-to-time converter 220, and a D flip-flop 230.
Operation of the conventional time-domain voltage comparator 200 configured as shown in FIG. 2 will be described below with reference to the circuit diagram of each of the first and second voltage-to-time converters 210 and 220.
The first voltage-to-time converter 210 and the second voltage-to-time converter 220 have the same circuit configuration as shown in FIG. 2. Operations of the first and second voltage-to-time converters 210 and 220 will be described below.
First, when a clock signal CLK is low, a PMOS M1 is turned on and an NMOS M3 is turned off. According to this fact, a voltage of a power supply terminal VDD is charged to a capacitor C through the PMOS M1, and the charged voltage is supplied to the gate terminal of a PMOS M2, by which the PMOS M2 is turned off. Therefore, an output OUT is maintained at a low state.
Conversely, when the clock signal CLK transits to high, the PMOS M1 is turned off and the NMOS M3 is turned on. The clock signal CLK of a high level is inverted through an inverter I1 to a low level and is commonly supplied to the gate terminals of NMOSes M5 and M6, by which the NMOSes M5 and M6 are turned off. At this time, a degree to which an NMOS M4 is turned on is determined by the magnitude of an input voltage Vin. If a high input voltage Vin is applied, the NMOS M4 is sufficiently turned on to have a low resistance value, and if a low input voltage Vin is applied, the NMOS M4 is insufficiently turned on to have a high resistance value.
At the same time, the voltage charged to the capacitor C gradually discharges through the NMOSes M3 and M4 and a resistor R. According to this fact, the PMOS M2 is slowly turned on, and the voltage of the power supply terminal VDD is outputted through the PMOS M2 and inverters I2 and I3 serially connected thereto. The output OUT becomes high.
If two voltage-to-time converters operating in this way are used, an output of one converter which receives a higher input voltage between two input voltages V+ and V− transits more quickly, and an output of the other inverter which receives a negative input voltage between the two input voltages V+ and V− transits more slowly.
After a difference in input voltage is converted into a difference in transition time through a series of above-described processes, two outputs converted in these ways are inputted to a data terminal D and a clock signal terminal of a D flip-flop D-F/F. As a consequence, it is possible to know an output of which one of the two converters has transited more quickly, based on outputs OUT and OUT of the D flip-flop D-F/F.
However, this type of comparator has two problems as described below, in the light of an offset.
First, if matching of the two voltage-to-time converts is not precisely implemented, even though the same input voltage is supplied, times during which the outputs transit become different, and due to this fact, an offset occurs.
Second, even when matching of the two voltage-to-time converts is precisely implemented, an offset is likely to occur due to a set-up time and a hold time as the inherent characteristics of the D flip-flop.